1. Field of the Invention
The present invention relates generally to semiconductor devices and manufacturing methods thereof and, more particularly, to structure of a dynamic memory device in which a so-called trench capacitor is employed as a capacitor, and a vertical MOS field effect transistor is formed as a transistor, and a method of manufacturing such a dynamic memory device.
2. Description of the Background Art
Recently, a higher degree of integration of semiconductor devices has been required, and accordingly, it becomes the greatest technical assignment to reduce the area of a memory cell storing 1-bit information in the semiconductor devices. In dynamic memory devices, the respective areas of a capacitor, drain and isolation region are required to be as small as possible. To satisfy this requirement, a dynamic memory device has conventionally been proposed in which a trench capacitor is adopted as a capacitor, a MOS field effect transistor is formed on a side surface of the same trench forming the capacitor therein, and an oxide film is utilized for an isolation region (See, e.g., IEDM85, pp.714-717.)
FIGS. 1A and 1B show one example of a conventional dynamic memory device. This dynamic memory device includes a p type epitaxial layer 2 formed on a p type silicon substrate 1, and a trench 3 formed in this p type epitaxial layer 2 and extending into silicon substrate 1. A second conductor layer 5 is formed at a portion of trench 3 located in silicon substrate 1, with a dielectric film 4 interposed therebetween. A first conductor layer 7 serving as a word line is formed at a portion of trench 3 located in epitaxial film 2, with a gate insulation film 6 interposed therebetween. An n type drain 8 serving as a bit line is formed on a surface of epitaxial layer 2 on peripheries of an opening of trench 3. Silicon substrate 1 and second conductor layer 5 interposing dielectric film 4 therebetween constitute a cell plate of a trench capacitor and a storage node, respectively.
A manufacture process of this dynamic memory device will now be described.
First, a silicon epitaxial layer 2 including p type impurities in a lower density than that of p type impurities included in a silicon substrate 1 is formed on silicon substrate 1. Only a portion of a surface of this silicon epitaxial layer which is to be isolated is selectively oxidized, to form an oxide film 9. Then, the resultant film is ion-implanted with n type impurities such as arsenic or the like and is also subjected to a thermal processing, so that drain 8 serving as a bit line is formed on the surface of silicon epitaxial layer 2.
Next, a hole extending from the surface of silicon epitaxial layer 2 to semiconductor substrate 1 is formed at a predetermined position, and a dielectric layer 4 such as a silicon oxide film, silicon nitride film or the like and a second conductor layer 5 formed of polysilicon and including n type impurities such as phosphorus or the like fill the hole halfway in silicon epitaxial layer 2. At this time, however, an upper end of dielectric film 4 is set to be lower than that of second conductor layer 5 so that second conductor layer 5 may become conductive with silicon epitaxial layer 2.
Then, a gate insulation film 6 is formed on the surface of silicon epitaxial layer 2 (including also a surface of drain 8), and then a first conductor layer 7 formed of polysilicon including phosphorus or the like is deposited thereon by a CVD (Chemical Vapor Deposition) or the like. The deposited layer is patterned to form a word line.
A memory cell having this structure constitutes a MOS field effect transistor including first conductor layer 7 as a gate electrode, drain 8 as a drain region and an upper portion of second conductor layer 5 as a source region. Accordingly, first conductor layer 7 serves as a word line for an input/output, drain 8 as a bit line for an input/output, and second conductor layer 5 as a storage node (a capacitor electrode), so that the structure thus formed operates as a memory cell like a normal dynamic memory device. In a semiconductor device having this structure, major portions of the MOS transistor, i.e., source/drain regions, a channel region and the like are formed outside the trench. More specifically, since an active layer of the MOS transistor is formed on the substrate side, an isolation between elements such as by an oxide film is required. In case where an isolation width decreases forcibly in order to reduce the area of an isolation region occupying the area of the memory cell, the capability and reliability of the transistor as an element might considerably deteriorate due to deterioration of isolation characteristics. To maintain excellent isolation characteristics, the proportion of the isolation region area to the area of the memory cell requires approximately 50% of the memory cell area. That is, the area approximately half the memory cell area should be used for isolation alone, resulting in the disadvantage that there is a limitation in reduction of the isolation region area.